1. Field of the Invention
The invention relates to a phase lock loop (PLL) circuit, and more particularly to an area efficient and low KVCO PLL circuit.
2. Description of the Related Art
PLL stands for Phase Lock Loop and is basically a closed loop frequency control system, wherein operation is based on the phase sensitive detection of phase differences between a feedback signal and a reference signal. A PLL circuit responds to both the frequency and the phase of input signals, automatically raising or lowering the frequency of a controlled oscillator until a feedback signal is matched to a reference signal in both frequency and phase. In simpler terms, a PLL compares the frequencies of two signals and produces a control signal which is proportional to the difference between the input frequencies. The control signal is used to drive a controlled oscillator, such as a voltage-controlled oscillator (VCO), which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the control signal may increase, driving the frequency in the opposite direction so as to reduce the error. Thus, the output is locked to the frequency of the reference signal. This reference signal could be derived from a crystal oscillator, which is very stable in frequency.
PLL circuits are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communications channel, or distribute clock timing pulses in digital logic designs such as microprocessors. The PLL with low gain value K of the controlled oscillator (i.e. the KVCO of the VCO) has several benefits. First of all, the jitter induced from control voltage Vctrl noise (e.g. reference spur, power noise couple) may be minimized. Second, loop filter capacitor size may be saved for a given bandwidth. Thus, both jitter performance and area would be beneficial from a low KVCO PLL design. However, low KVCO PLL may bring small frequency adjusting range if available Vctrl range is small, which is likely to happen in advanced technology. For example, in a pure 1.2V design, maximum available Vctrl range is only about 0.6V. To cover process variation and accommodate GHz-level output frequency, low KVCO may not be obtainable and KVCO is inevitably approaching several GHz % Volt range. Therefore, an area efficient and low KVCO PLL circuit solving the above-mentioned problems is highly desired.